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Specific Grant Agreement European Low-Power Microprocessor Technologies 2020, ID: EuroHPC-2020-02
bis 01.01.2022
Specific Challenge:
Within the Framework Partnership Agreement in European low-power microprocessor technologies awarded in 2017, the selected consortium will be invited to submit a Research and Innovation Action proposal for the second phase of the design and development of European low-power processors and related technologies for extreme-scale, high-performance big-data, AI and emerging applications, in accordance with the research roadmap defined in the respective FPA.

In particular, the proposal will build on the results of the Phase 1 of the European Processor Initiative (EPI), and is expected to cover the following topics:

1. Development of the second generation of low-power general purpose processing system units. Generate the functional and non-functional requirements (using representative HPC and big-data benchmarks, emerging applications specifications (in the automotive sector for example), and targeting maximum energy-efficiency and reliability; design the architecture of the processing system units; verify, tape-out, validate, test and bring up the processing system units; develop the required firmware and system software leveraging, as much as possible, on open source efforts and solutions.

2. Development of the second generation of low-power processing system units for application acceleration. Generate their functional and non-functional requirements (using relevant representative HPC and big data benchmarks and emerging applications) and design their architecture to accelerate specific HPC and big data applications, including as edge and embedded automotive applications or other emerging applications. The applications must have high-volume potential. Processing units will be realised as standalone components, distributed collaborating systems or IP-blocks, and will include stand-alone open RISC V hardware approaches for accelerators with connectivity not limited to the EPI processing units, addressing a large number of application areas. Work in this topic is required to interface with topic a) in order to achieve maximum interoperability (including IP-block interfacing) and roadmap synchronisation.

3. Validation of the first generation of low-power processing system units developed in Phase 1 (and Phase 2). Finalize the required firmware and system software leveraging, as much as possible, on open source efforts and solutions; development and integration of the boards/blades and test benches to demonstrate the processing units and accelerators developed in Phase 1 (and Phase 2) of EPI with the porting of representative sets of real-life kernels for the chosen application(s). This will address also the integration and interconnection of the EPI hardware ecosystem with other approaches.

4. Support for a hardware and software development platform common to different processor and accelerator types. This platform should be accessible by a wide range of interested parties. Support should also be directed towards maximising early on the uptake by users of processor and accelerator technology developed in Phases 1 and 2 of EPI for testing purposes.

The developed technologies will demonstrate the synergies between HPC at the exascale level and scalability to distributed collaborating systems in emerging computing applications, in the automotive sector for example. The designs should follow a modular approach that would allow a rapid scale-up or scale-down. Sustainability and economic viability of the developed solutions are key aspects.

Wherever appropriate in order to address specific technology needs and/or activities, the consortium should seek additional partners to join the FPA consortium, provided they respect the objectives of the project.

Wherever appropriate, the proposal could seek synergies and co-financing from relevant national or regional research and innovation programmes, including structural funds addressing smart specialisation. Work combining different sources of financing should include a concrete financial plan detailing the use of these funding sources for the different parts of the activities.

Considering the specific objectives of the call for proposals and the fact that these calls concern areas of critical importance for the security of Union and the Digital Single Market and may pose potential risk to ensuring European technological autonomy in line with Article 9(5) of the Rules for Participation, the EuroHPC JU may limit the participation of legal entities established in associated countries and legal entities established in the EU but controlled from third countries.

Expected Impact:
Proposals should describe how the proposed work will contribute to the impacts listed below and include a baseline, targets and metrics to measure impact.

o Contribution to the realisation of the EuroHPC JU's overall and specific objectives
o Strengthening scientific leadership as well as the competitiveness and innovation potential of European industry, contributing to a sustainable exascale HPC supply ecosystem in Europe and ensuring European technological autonomy in this field
o Provide European industry with a competitive edge in processor technology with potential for a wide range of applications from engineering, science and bio-medical to automotive, manufacturing, finance and emerging big-data and smart objects fields
o Leveraging the efforts on the European low power processing technologies (in particular the European Processor Initiative) and contributing to the realisation of future exascale system architectures based on such technologies
o Creation, promotion and exploitation potential of European IP

Further Information: